398 search results - page 21 / 80 » Hardware Reuse at the Behavioral Level |
VTS
2003
IEEE
14 years 1 months ago
2003
IEEE
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
ECAI
2004
Springer
14 years 1 months ago
2004
Springer
Recent years have seen considerable developments in modeling techniques for automatic fault location in programs. However, much of this research considered the models from a standa...
CORR
2008
Springer
13 years 8 months ago
2008
Springer
Pipelining is a well understood and often used implementation technique for increasing the performance of a hardware system. We develop several SystemC/C++ modeling techniques tha...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
System level synthesis is widely seen as the solution for closing the productivity gap in system design. High level system models are used in system level design for early design ...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...