Sciweavers

398 search results - page 47 / 80
» Hardware Reuse at the Behavioral Level
Sort
View
ICCD
2004
IEEE
97views Hardware» more  ICCD 2004»
14 years 5 months ago
Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution
1 Many computer security threats involve execution of unauthorized foreign code on the victim computer. Viruses, network and email worms, Trojan horses, backdoor programs used in ...
A. Murat Fiskiran, Ruby B. Lee
MTV
2006
IEEE
98views Hardware» more  MTV 2006»
14 years 2 months ago
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, archite...
Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy...
ICCAD
1996
IEEE
141views Hardware» more  ICCAD 1996»
14 years 20 days ago
An observability-based code coverage metric for functional simulation
Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the design...
Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer
ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
14 years 2 days ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...
DSD
2010
IEEE
137views Hardware» more  DSD 2010»
13 years 6 months ago
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...