398 search results - page 75 / 80 » Hardware Reuse at the Behavioral Level |
ISCA
2002
IEEE
14 years 8 days ago
2002
IEEE
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
DSN
2007
IEEE
13 years 11 months ago
2007
IEEE
Although there are various ways to exploit software vulnerabilities for malicious attacks, the attacks always result in unexpected behavior in program execution, deviating from wh...
CGO
2007
IEEE
14 years 1 months ago
2007
IEEE
Modern memory systems play a critical role in the performance of applications, but a detailed understanding of the application behavior in the memory system is not trivial to atta...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
ASPLOS
1998
ACM
13 years 11 months ago
1998
ACM
Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...