Sciweavers

398 search results - page 77 / 80
» Hardware Reuse at the Behavioral Level
Sort
View
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 4 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
CODES
2009
IEEE
14 years 2 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
DATE
2008
IEEE
74views Hardware» more  DATE 2008»
14 years 1 months ago
A Design-for-Diagnosis Technique for SRAM Write Drivers
∗ Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, a...
Alexandre Ney, Patrick Girard, Serge Pravossoudovi...
CAV
2005
Springer
173views Hardware» more  CAV 2005»
14 years 27 days ago
Building Your Own Software Model Checker Using the Bogor Extensible Model Checking Framework
Model checking has proven to be an effective technology for verification and debugging in hardware and more recently in software domains. We believe that recent trends in both th...
Matthew B. Dwyer, John Hatcliff, Matthew Hoosier, ...
ROBOCUP
2004
Springer
133views Robotics» more  ROBOCUP 2004»
14 years 21 days ago
Towards a League-Independent Qualitative Soccer Theory for RoboCup
The paper discusses a top-down approach to model soccer knowledge, as it can be found in soccer theory books. The goal is to model soccer strategies and tactics in a way that they ...
Frank Dylla, Alexander Ferrein, Gerhard Lakemeyer,...