Sciweavers

398 search results - page 7 / 80
» Hardware Reuse at the Behavioral Level
Sort
View
FPL
2009
Springer
104views Hardware» more  FPL 2009»
13 years 12 months ago
A multi-layered XML schema and design tool for reusing and integrating FPGA IP
Reconfigurable computing systems remain difficult to use and program. One way to increase design productivity for these systems is through reuse of previously developed and veri...
Adam Arnesen, Nathan Rollins, Michael J. Wirthlin
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
14 years 29 days ago
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring
— Security is emerging as an important concern in embedded system design. The security of embedded systems is often compromised due to vulnerabilities in “trusted” software t...
Divya Arora, Srivaths Ravi, Anand Raghunathan, Nir...
IWMM
2009
Springer
130views Hardware» more  IWMM 2009»
14 years 1 months ago
A component model of spatial locality
Good spatial locality alleviates both the latency and bandwidth problem of memory by boosting the effect of prefetching and improving the utilization of cache. However, convention...
Xiaoming Gu, Ian Christopher, Tongxin Bai, Chengli...
ITC
2000
IEEE
110views Hardware» more  ITC 2000»
13 years 11 months ago
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
Ramesh Karri, Kaijie Wu
FPL
2001
Springer
96views Hardware» more  FPL 2001»
13 years 12 months ago
System Level Tools for DSP in FPGAs
Abstract. Visual data ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal ow gra...
James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey ...