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ICCD
2002
IEEE
101views Hardware» more  ICCD 2002»
14 years 4 months ago
Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering
Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Popular repre...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
ATVA
2006
Springer
100views Hardware» more  ATVA 2006»
13 years 11 months ago
A Fine-Grained Fullness-Guided Chaining Heuristic for Symbolic Reachability Analysis
Chaining can reduce the number of iterations required for symbolic state-space generation and model-checking, especially in Petri nets and similar asynchronous systems, but require...
Ming-Ying Chung, Gianfranco Ciardo, Andy Jinqing Y...
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
13 years 9 months ago
An LP-based methodology for improved timing-driven placement
— A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formu...
Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanya...
ACMMSP
2004
ACM
101views Hardware» more  ACMMSP 2004»
14 years 27 days ago
Metrics and models for reordering transformations
Irregular applications frequently exhibit poor performance on contemporary computer architectures, in large part because of their inefficient use of the memory hierarchy. Runtime ...
Michelle Mills Strout, Paul D. Hovland
ICCAD
1997
IEEE
121views Hardware» more  ICCAD 1997»
13 years 11 months ago
Adaptive methods for netlist partitioning
An algorithm that remains in use at the core of many partitioning systems is the Kernighan-Lin algorithm and a variant the Fidducia-Matheysses (FM) algorithm. To understand the FM...
Wray L. Buntine, Lixin Su, A. Richard Newton, Andr...