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» Hardware Support for Control Transfers in Code Caches
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DATE
2010
IEEE
130views Hardware» more  DATE 2010»
13 years 11 months ago
Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller
Abstract—Supporting Distributed Shared Memory (DSM) is essential for multi-core Network-on-Chips for the sake of reusing huge amount of legacy code and easy programmability. We p...
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming C...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
14 years 1 months ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...
CASES
2006
ACM
14 years 1 months ago
A case study of multi-threading in the embedded space
The continuing miniaturization of technology coupled with wireless networks has made it feasible to physically embed sensor network systems into the environment. Sensor net proces...
Greg Hoover, Forrest Brewer, Timothy Sherwood
PLDI
2012
ACM
11 years 10 months ago
Language-based control and mitigation of timing channels
We propose a new language-based approach to mitigating timing channels. In this language, well-typed programs provably leak only a bounded amount of information over time through ...
Danfeng Zhang, Aslan Askarov, Andrew C. Myers
MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
13 years 5 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...