230 search results - page 24 / 46 » Hardware Support for Control Transfers in Code Caches |
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Retargetable C compilers are key components of today’s embedded processor design platforms for quickly obtaining compiler support and performing early processor architecture exp...
SPAA
2004
ACM
14 years 29 days ago
2004
ACM
We present the Buffer Heap (BH), a cache-oblivious priority queue that supports Delete-Min, Delete, and Decrease-Key operations in O( 1 B log2 N B ) amortized block transfers fro...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
A simple and low-cost approach to supporting snoopy cache coherence is to logically embed a unidirectional ring in the network of a multiprocessor, and use it to transfer snoop me...
SIGMETRICS
1996
ACM
13 years 11 months ago
1996
ACM
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...
HPCA
1998
IEEE
13 years 11 months ago
1998
IEEE
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable that microprocessors will exploit having multiple parallel threads. To achieve t...