230 search results - page 5 / 46 » Hardware Support for Control Transfers in Code Caches |
ICPP
2009
IEEE
13 years 5 months ago
2009
IEEE
The emergence of multicore processors raises the need to efficiently transfer large amounts of data between local processes. MPICH2 is a highly portable MPI implementation whose l...
ISMVL
2003
IEEE
14 years 23 days ago
2003
IEEE
A new asynchronous data transfer scheme using multiple-valued 2-color 1-phase coding, called a bidirectional data transfer scheme, is proposed for a highperformance and low-power ...
CODES
2008
IEEE
14 years 1 months ago
2008
IEEE
Open Core Protocol (OCP) is a standard on-chip core interface specification. The current release is flexible and configurable to support the communication needs of a wide range...
CODES
2001
IEEE
13 years 11 months ago
2001
IEEE
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...
TC
2011
13 years 1 months ago
2011
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...