86 search results - page 5 / 18 » Hardware Support for Interval Arithmetic |
FCCM
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, ...
ASIACRYPT
2001
Springer
14 years 2 days ago
2001
Springer
Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all...
ASAP
2002
IEEE
14 years 16 days ago
2002
IEEE
This paper introduces PAPA: Packed Arithmetic on a Prefix Adder, a new approach to parallel prefix adder design that supports a wide variety of packed arithmetic computations, inc...
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
FPL
2007
Springer
14 years 1 months ago
2007
Springer
In this paper we present Minibit+, an approach that optimizes the bit-widths of fixed-point and floating-point designs, while guaranteeing accuracy. Our approach adopts differen...