59 search results - page 9 / 12 » Hardware Support for Relaxed Concurrency Control in Transact... |
CACM
2011
13 years 1 months ago
2011
Software Transactional Memory (STM) promises to simplify concurrent programming without requiring specific hardware support. Yet, STM’s credibility lies on the extent to which ...
ASPLOS
2010
ACM
14 years 1 months ago
2010
ACM
With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades...
ASAP
2007
IEEE
13 years 8 months ago
2007
IEEE
A novel object-oriented processor is proposed in this paper, which provides support for object addressing, message passing and dynamic memory management. Object running on this pr...
RTSS
2007
IEEE
14 years 1 months ago
2007
IEEE
The integration phase of real-time COTS-based systems is often problematic because when multiple tasks run concurrently, the interference at the bus level between cache fetching a...
ASPLOS
2008
ACM
13 years 8 months ago
2008
ACM
Standard concurrency control mechanisms offer a trade-off: Transactional memory approaches maximize concurrency, but suffer high overheads and cost for retrying in the case of act...