3902 search results - page 10 / 781 » Hardware Synthesis from C C Models |
DSD
2006
IEEE
13 years 11 months ago
2006
IEEE
We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four bas...
DSD
2006
IEEE
14 years 1 months ago
2006
IEEE
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
ICES
2010
Springer
13 years 5 months ago
2010
Springer
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
IPPS
2003
IEEE
14 years 29 days ago
2003
IEEE
To cope with the increasing demand for higher computational power and flexibility, dynamically reconfigurable blocks become an important part inside a system-on-chip. Several meth...