3902 search results - page 139 / 781 » Hardware Synthesis from C C Models |
114
Voted
DATE
2004
IEEE
15 years 7 months ago
2004
IEEE
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
140
Voted
DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
Reflection and automated introspection of a design in system level design frameworks are seen as necessities for the CAD tools to manipulate the designs within the tools. These f...
135
Voted
INFOCOM
2007
IEEE
15 years 10 months ago
2007
IEEE
— This paper argues for the need to address the issue of multi-channel network performance under constraints on channel switching. We present examples from emergent directions in...
129
Voted
ISCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
114
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ICSE
2004
IEEE-ACM
16 years 3 months ago
2004
IEEE-ACM
We have extended the software model checker BLAST to automatically generate test suites that guarantee full coverage with respect to a given predicate. More precisely, given a C p...