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ISQED
2006
IEEE
90views Hardware» more  ISQED 2006»
14 years 3 months ago
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykr...
ASPDAC
2000
ACM
99views Hardware» more  ASPDAC 2000»
14 years 1 months ago
Reuse and protection of intellectual property in the SpecC system
— In system-level design, the key to cope with the complexities involved with System-on-Chip (SOC) designs, is the reuse of Intellectual Property (IP). With the increasing demand...
Rainer Dömer, Daniel Gajski
BMCBI
2008
129views more  BMCBI 2008»
13 years 9 months ago
An analytic and systematic framework for estimating metabolic flux ratios from 13C tracer experiments
Background: Metabolic fluxes provide invaluable insight on the integrated response of a cell to environmental stimuli or genetic modifications. Current computational methods for e...
Ari Rantanen, Juho Rousu, Paula Jouhten, Nicola Za...
CDC
2009
IEEE
137views Control Systems» more  CDC 2009»
14 years 1 months ago
Discretization of Linear Fractional Representations of LPV systems
Abstract— Commonly, controllers for Linear ParameterVarying (LPV) systems are designed in continuous-time using a Linear Fractional Representation (LFR) of the plant. However, th...
Roland Tóth, Marco Lovera, Peter S. C. Heub...