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INTEGRATION
2008
183views more  INTEGRATION 2008»
15 years 3 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
137
Voted
SP
2003
IEEE
121views Security Privacy» more  SP 2003»
15 years 8 months ago
Specifying and Verifying Hardware for Tamper-Resistant Software
We specify a hardware architecture that supports tamper-resistant software by identifying an “idealized” hich gives the abstracted actions available to a single user program. ...
David Lie, John C. Mitchell, Chandramohan A. Thekk...
SIGMETRICS
2005
ACM
104views Hardware» more  SIGMETRICS 2005»
15 years 9 months ago
Message delay in MANET
A generic stochastic model with only two input parameters is introduced to evaluate the message delay in mobile ad hoc networks (MANETs) where nodes may relay messages. The Laplac...
Robin Groenevelt, Philippe Nain, Ger Koole
ICCAD
2001
IEEE
102views Hardware» more  ICCAD 2001»
16 years 11 days ago
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...
ICCAD
1997
IEEE
142views Hardware» more  ICCAD 1997»
15 years 7 months ago
Library-less synthesis for static CMOS combinational logic circuits
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullel...