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FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
14 years 4 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
ISCAS
2008
IEEE
195views Hardware» more  ISCAS 2008»
14 years 2 months ago
Multi-view depth video coding using depth view synthesis
— Depth information indicates the distance of an object in the three dimensional (3D) scene from the camera view-point, typically represented by eight bits. Since the depth map i...
Sang-Tae Na, Kwan-Jung Oh, Cheon Lee, Yo-Sung Ho
CAIP
2009
Springer
202views Image Analysis» more  CAIP 2009»
13 years 5 months ago
Near-Regular Texture Synthesis
This paper describes a method for seamless enlargement or editing of difficult colour textures containing simultaneously both regular periodic and stochastic components. Such textu...
Michal Haindl, Martin Hatka
ASPDAC
2000
ACM
120views Hardware» more  ASPDAC 2000»
13 years 12 months ago
Data memory minimization by sharing large size buffers
- This paper presents software synthesis techniques to deal with non-primitive data type from graphical dataflow programs based on the synchronous dataflow (SDF) model. Non-primiti...
Hyunok Oh, Soonhoi Ha
ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu