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» Hardware Synthesis from Term Rewriting Systems
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DATE
2006
IEEE
118views Hardware» more  DATE 2006»
14 years 3 months ago
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit
Multimedia and communication algorithms from embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-poin...
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Hei...
TEI
2012
ACM
257views Hardware» more  TEI 2012»
12 years 4 months ago
Beyond affordance: tangibles' hybrid nature
A prevalent assumption behind interface approaches that employ physical means of interaction is that this leverages users’ prior knowledge from the real world. This paper scruti...
Eva Hornecker
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
14 years 3 months ago
Fixed points for multi-cycle path detection
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
Vijay D'Silva, Daniel Kroening
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
14 years 1 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
ICCAD
1997
IEEE
69views Hardware» more  ICCAD 1997»
14 years 1 months ago
Speeding up technology-independent timing optimization by network partitioning
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita