Sciweavers

974 search results - page 164 / 195
» Hardware Synthesis from Term Rewriting Systems
Sort
View
DAC
2004
ACM
14 years 11 months ago
Virtual memory window for application-specific reconfigurable coprocessors
Reconfigurable Systems-on-Chip (SoCs) on the market consist of full-fledged processors and large Field-Programmable Gate-Arrays (FPGAs). The latter can be used to implement the sy...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
ISCA
2010
IEEE
229views Hardware» more  ISCA 2010»
13 years 8 months ago
Understanding sources of inefficiency in general-purpose chips
Due to their high volume, general-purpose processors, and now chip multiprocessors (CMPs), are much more cost effective than ASICs, but lag significantly in terms of performance a...
Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Az...
SENSYS
2006
ACM
14 years 4 months ago
Run-time dynamic linking for reprogramming wireless sensor networks
From experience with wireless sensor networks it has become apparent that dynamic reprogramming of the sensor nodes is a useful feature. The resource constraints in terms of energ...
Adam Dunkels, Niclas Finne, Joakim Eriksson, Thiem...
ISLPED
2004
ACM
110views Hardware» more  ISLPED 2004»
14 years 3 months ago
Reducing pipeline energy demands with local DVS and dynamic retiming
The quadratic relationship between voltage and energy has made dynamic voltage scaling (DVS) one of the most powerful techniques to reduce system power demands. Recently, techniqu...
Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Au...
DAC
2009
ACM
14 years 11 months ago
Context-sensitive timing analysis of Esterel programs
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty, Abh...