974 search results - page 48 / 195 » Hardware Synthesis from Term Rewriting Systems |
DAC
1989
ACM
14 years 28 days ago
1989
ACM
- New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques ...
ISSS
1995
IEEE
14 years 12 days ago
1995
IEEE
In this paper we brie
y describe a set of designs that can serve as examples for High Level Synthesis (HLS) systems. The designs vary in complexity from simple behavioral nite st...
CL
2008
Springer
13 years 9 months ago
2008
Springer
Currently available application frameworks that target the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for m...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, a...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...