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» Hardware and Petri Nets: Application to Asynchronous Circuit...
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ICCAD
2008
IEEE
150views Hardware» more  ICCAD 2008»
14 years 6 months ago
Performance estimation and slack matching for pipelined asynchronous architectures with choice
— This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the pro...
Gennette Gill, Vishal Gupta, Montek Singh
ICCAD
1999
IEEE
80views Hardware» more  ICCAD 1999»
14 years 2 months ago
What is the cost of delay insensitivity?
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous spee...
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, ...
CPE
2000
Springer
369views Hardware» more  CPE 2000»
14 years 2 months ago
Petri Net Modelling and Performability Evaluation with TimeNET 3.0
Abstract. This paper presents TimeNET, a software tool for the modelling and performability evaluation using stochastic Petri nets. The tool has been designed especially for models...
Armin Zimmermann, Jörn Freiheit, Reinhard Ger...
DAC
1996
ACM
14 years 1 months ago
Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis
This paper proposes a state encoding method for asynchronous circuits based on the theory of regions. A region in a Transition System is a set of states that "behave uniforml...
Jordi Cortadella, Michael Kishinevsky, Alex Kondra...
APN
2005
Springer
14 years 3 months ago
Determinate STG Decomposition of Marked Graphs
STGs give a formalism for the description of asynchronous circuits based on Petri nets. To overcome the state explosion problem one may encounter during circuit synthesis, a nondet...
Mark Schäfer, Walter Vogler, Petr Jancar