Sciweavers

951 search results - page 27 / 191
» Hardware design experiences in ZebraNet
Sort
View
DATE
2004
IEEE
210views Hardware» more  DATE 2004»
13 years 11 months ago
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a...
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru N...
ASPDAC
2007
ACM
88views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Voltage Island Generation under Performance Requirement for SoC Designs
Using multiple supply voltages on a SoC design is an efficient way to achieve low power. However, it may lead to a complex power network and a huge number of level shifters if we j...
Wai-Kei Mak, Jr-Wei Chen
DATE
2009
IEEE
115views Hardware» more  DATE 2009»
13 years 11 months ago
Customizing IP cores for system-on-chip designs using extensive external don't-cares
Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditio...
Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
OSDI
1994
ACM
13 years 9 months ago
The Design and Evaluation of a Shared Object System for Distributed Memory Machines
This paper describes the design and evaluation of SAM, a shared object system for distributed memory machines. SAM is a portable run-time system that provides a global name space ...
Daniel J. Scales, Monica S. Lam
EURODAC
1995
IEEE
128views VHDL» more  EURODAC 1995»
13 years 11 months ago
Closeness metrics for system-level functional partitioning
An important system design task is the partitioning of system functionality for implementation among multiple system components, including partitions among hardware and software c...
Frank Vahid, Daniel D. Gajski