951 search results - page 5 / 191 » Hardware design experiences in ZebraNet |
BCS
2008
13 years 9 months ago
2008
Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...
ITC
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and tes...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
In this paper, we propose a new internally buffered crossbar (IBC) switching architecture where the input and output distributed schedulers are embedded inside the crossbar fabric...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Designers of factory automation applications increasingly demand for tools for rapid prototyping of hardware extensions to existing systems and verification of resulting behavior...