421 search results - page 5 / 85 » Hardware efficient architectures for Eigenvalue computation |
CODES
2006
IEEE
14 years 5 days ago
2006
IEEE
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
With the projected significant growth in mobile internet and multimedia services, there is a strong demand for nextgeneration appliances capable of wireless image communication. O...
ICONS
2008
IEEE
14 years 2 months ago
2008
IEEE
DL systems with bilinear structure recently became an important base for cryptographic protocols such as identity-based encryption (IBE). Since the main computational task is the ...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, an efficient VLSI architecture for a fast computation of the 2-D discrete wavelet transform (DWT) is proposed. The architecture employing a three-stage cascade in p...
ICES
2010
Springer
13 years 6 months ago
2010
Springer
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...