355 search results - page 34 / 71 » Hardware implementation of a novel genetic algorithm |
HOTI
2002
IEEE
14 years 20 days ago
2002
IEEE
High-performance input-queued switches require highspeed scheduling algorithms while maintaining good performance. Various round-robin scheduling algorithms for Virtual Output Que...
ISCAS
1999
IEEE
13 years 12 months ago
1999
IEEE
High-level power design presents a complex, multiobjective problem that involves the simultaneous optimisation of competing criteria such as speed, area and power. It is difficult...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
ACSD
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper test selection strategies in formal conformance testing are considered. As the testing conformance relation we use the ioco relation, and extend the previously prese...