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» Hardware implementation of a novel genetic algorithm
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DATE
2009
IEEE
137views Hardware» more  DATE 2009»
14 years 2 months ago
aEqualized: A novel routing algorithm for the Spidergon Network On Chip
—We present the aEqualized routing algorithm: a novel algorithm for the Spidergon Network on Chip. AEqualized combines the well known aFirst and aLast algorithms proposed in lite...
Nicola Concer, Salvatore Iamundo, Luciano Bononi
ASPDAC
2005
ACM
133views Hardware» more  ASPDAC 2005»
13 years 9 months ago
A novel O(n) parallel banker's algorithm for System-on-a-Chip
This paper proposes a novel O(n) Parallel Banker’s Algorithm (PBA) with a best-case run-time of O(1), reduced from an ¢¤£¦¥¨§© run-time complexity of the original Ban...
Jaehwan John Lee, Vincent John Mooney III
JDCTA
2010
102views more  JDCTA 2010»
13 years 2 months ago
A Novel Pixel Line Based Algorithm for Line Generation
Straight line is the most basic element of graphics, and it is of great significance to study fast algorithm of line generating. On the basis of Bresenham algorithm, this paper co...
Yu-rong Li, Fu-guo Dong
ISCAS
2005
IEEE
138views Hardware» more  ISCAS 2005»
14 years 1 months ago
Modeling of MOS transistors based on genetic algorithm and simulated annealing
— A novel method to extract the efficient model for Metal-Oxide-Semiconductor (MOS) transistors in order to satisfy a specific accuracy is presented. The approach presented here ...
Mohammad Taherzadeh-Sani, Ali Abbasian, Behnam Ame...
ICES
2010
Springer
106views Hardware» more  ICES 2010»
13 years 5 months ago
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application
Abstract. In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues ar...
Jaroslav Skarvada, Zdenek Kotásek, Josef St...