111 search results - page 8 / 23 » Hardware scheduling support in SMP architectures |
ICCD
2002
IEEE
14 years 3 months ago
2002
IEEE
Embedded processors are increasingly deployed in applications requiring high performance with good real-time characteristics whilst being low power. Parallelism has to be extracte...
MICRO
1993
IEEE
13 years 10 months ago
1993
IEEE
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
MICRO
1991
IEEE
13 years 10 months ago
1991
IEEE
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
ANCS
2006
ACM
14 years 21 days ago
2006
ACM
Buffered crossbar switches are a special type of crossbar switches. In such a switch, besides normal input queues and output queues, a small buffer is associated with each crosspo...
INFOCOM
2000
IEEE
13 years 11 months ago
2000
IEEE
-In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine-grained quality of service (QoS) gu...