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CODES
2007
IEEE
14 years 2 months ago
Performance improvement of block based NAND flash translation layer
With growing capacities of flash memories, an efficient layer to manage read and write access to flash is required. NFTL is a widely used block based flash translation layer de...
Siddharth Choudhuri, Tony Givargis
ICAS
2008
IEEE
200views Robotics» more  ICAS 2008»
14 years 2 months ago
Connectivity of Thetis, a Distributed Hybrid Simulator, with a Mixed Control Architecture
—The purpose of this paper is to present the linkage of Thetis (a real time multi-vehicles hybrid simulator for heterogeneous vehicles) with a control architecture for the manage...
Olivier Parodi, Abdellah El Jalaoui, David Andreu
CODES
2008
IEEE
14 years 2 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid
ICCAD
1996
IEEE
119views Hardware» more  ICCAD 1996»
14 years 19 days ago
An algorithm for synthesis of system-level interface circuits
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with ...
Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu
CODES
2007
IEEE
14 years 2 months ago
Complex task activation schemes in system level performance analysis
The design and analysis of today’s complex real-time systems requires advanced methods. Due to ever growing functionality, hardware complexity and component interaction, applyin...
Wolfgang Haid, Lothar Thiele