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MICRO
2009
IEEE
326views Hardware» more  MICRO 2009»
14 years 2 months ago
DDT: design and evaluation of a dynamic program analysis for optimizing data structure usage
Data structures define how values being computed are stored and accessed within programs. By recognizing what data structures are being used in an application, tools can make app...
Changhee Jung, Nathan Clark
CF
2011
ACM
12 years 7 months ago
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors
Dynamic Information Flow Tracking (DIFT) is a powerful technique that can protect unmodified binaries from a broad range of vulnerabilities such as buffer overflow and code inj...
Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazal...
IEEEPACT
2007
IEEE
14 years 1 months ago
Performance Portable Optimizations for Loops Containing Communication Operations
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...
Costin Iancu, Wei Chen, Katherine A. Yelick
MICRO
2007
IEEE
128views Hardware» more  MICRO 2007»
14 years 1 months ago
A Framework for Providing Quality of Service in Chip Multi-Processors
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse i...
Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer
ISCA
2010
IEEE
236views Hardware» more  ISCA 2010»
14 years 16 days ago
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
Enric Herrero, José González, Ramon ...