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» Hardware support for code integrity in embedded processors
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ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
13 years 12 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 12 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
KBSE
2005
IEEE
14 years 1 months ago
Locating faulty code using failure-inducing chops
Software debugging is the process of locating and correcting faulty code. Prior techniques to locate faulty code either use program analysis techniques such as backward dynamic pr...
Neelam Gupta, Haifeng He, Xiangyu Zhang, Rajiv Gup...
HIPEAC
2005
Springer
14 years 1 months ago
Memory-Centric Security Architecture
Abstract. This paper presents a new security architecture for protecting software confidentiality and integrity. Different from the previous process-centric systems designed for ...
Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee
ISCA
2008
IEEE
148views Hardware» more  ISCA 2008»
14 years 2 months ago
Atomic Vector Operations on Chip Multiprocessors
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Y...