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» Hardware support for code integrity in embedded processors
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FPL
2007
Springer
176views Hardware» more  FPL 2007»
14 years 1 months ago
ReconOS: An RTOS supporting Hard- and Software Threads
Modern platform FPGAs integrate fine-grained reconfigurable logic with processor cores and allow the creation of complete configurable systems-on-chip. However, design methodol...
Enno Lübbers, Marco Platzner
DAC
2006
ACM
13 years 11 months ago
IMPRES: integrated monitoring for processor reliability and security
Security and reliability in processor based systems are concerns requiring adroit solutions. Security is often compromised by code injection attacks, jeopardizing even `trusted so...
Roshan G. Ragel, Sri Parameswaran
ASYNC
1998
IEEE
122views Hardware» more  ASYNC 1998»
13 years 11 months ago
A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...
Martin Benes, Steven M. Nowick, Andrew Wolfe
ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
14 years 28 days ago
Compiler based exploration of DSP energy savings by SIMD operations
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
Markus Lorenz, Peter Marwedel, Thorsten Dräge...
ISSS
2000
IEEE
109views Hardware» more  ISSS 2000»
13 years 11 months ago
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors
The paper presents a novel software-pipelining algorithm suitable for optimizing compilers targeting embedded VLIW processors. The proposed algorithm is different from previous ap...
Cagdas Akturan, Margarida F. Jacome