734 search results - page 12 / 147 » Hardware support for code integrity in embedded processors |
137
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CODES
2008
IEEE
15 years 9 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
140
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CODES
2001
IEEE
15 years 6 months ago
2001
IEEE
The paper proposes a novel software-pipelining algorithm, Register Sensitive Force Directed Retiming Algorithm (RSFDRA), suitable for optimizing compilers targeting embedded VLIW ...
141
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EMSOFT
2004
Springer
15 years 8 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
161
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CODES
2003
IEEE
15 years 8 months ago
2003
IEEE
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
149
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EMSOFT
2005
Springer
15 years 8 months ago
2005
Springer
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...