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» Hardware support for code integrity in embedded processors
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ICMCS
2006
IEEE
113views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Enhanced Architectural Support for Variable-Length Decoding
This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves o...
Mohanarajah Sinnathamby, Subramania Sudharsanan, N...
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
13 years 5 months ago
Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels
Wide Single Instruction, Multiple Thread (SIMT) architectures often require a static allocation of thread groups that are executed in lockstep throughout the entire application ker...
Michael Steffen, Joseph Zambreno
CODES
2005
IEEE
14 years 1 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
ISCAS
2002
IEEE
111views Hardware» more  ISCAS 2002»
14 years 17 days ago
CASCADE - configurable and scalable DSP environment
As the complexity of embedded systems grows rapidly, it is common to accelerate critical tasks with hardware. Designers usually use off-the-shelf components or licensed IP cores t...
Tay-Jyi Lin, Chein-Wei Jen
ICCAD
2010
IEEE
126views Hardware» more  ICCAD 2010»
13 years 5 months ago
Characterizing the lifetime reliability of manycore processors with core-level redundancy
With aggressive technology scaling, integrated circuits suffer from everincreasing wearout effects and their lifetime reliability has become a serious concern for the industry. Fo...
Lin Huang, Qiang Xu