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» Heterogeneous behavioral hierarchy for system level designs
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LCTRTS
2007
Springer
14 years 1 months ago
Interface synthesis for heterogeneous multi-core systems from transaction level models
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
Hansu Cho, Samar Abdi, Daniel Gajski
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
14 years 4 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 7 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
IJCAI
2001
13 years 8 months ago
Heterogeneity in the Coevolved Behaviors of Mobile Robots: The Emergence of Specialists
Many mobile robot tasks can be most efficiently solved when a group of robots is utilized. The type of organization, and the level of coordination and communication within a team ...
Mitchell A. Potter, Lisa Meeden, Alan C. Schultz
HPCA
2008
IEEE
14 years 7 months ago
System level analysis of fast, per-core DVFS using on-chip switching regulators
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, Dav...