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DAC
2010
ACM
15 years 10 months ago
Eyecharts: constructive benchmarking of gate sizing heuristics
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla...
CGO
2004
IEEE
15 years 10 months ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
WCE
2007
15 years 7 months ago
Heuristic Based Approach of Cell Formation Considering Operation Sequence
—This paper presents, a two-stage heuristic based procedure for generating part family and machine cell formation in Cellular Manufacturing System. It decreases exceptional eleme...
Amit Rai Dixit, P. K. Mishra
IPPS
2010
IEEE
15 years 4 months ago
Offline library adaptation using automatically generated heuristics
Automatic tuning has emerged as a solution to provide high-performance libraries for fast changing, increasingly complex computer architectures. We distinguish offline adaptation (...
Frédéric de Mesmay, Yevgen Voronenko...
DAC
1999
ACM
16 years 7 months ago
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting
We illustrate how technical contributions in the VLSI CAD partitioning literature can fail to provide one or more of: (i) reproducible results and descriptions, (ii) an enabling a...
Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Ken...