43 search results - page 8 / 9 » Hiding Cache Miss Penalty Using Priority-based Execution for... |
SBACPAD
2009
IEEE
14 years 2 months ago
2009
IEEE
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
PDP
2010
IEEE
13 years 12 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
EDCC
2006
Springer
13 years 11 months ago
2006
Springer
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
CAINE
2006
13 years 9 months ago
2006
The synergy of software and hardware leads to efficient application expression profile (AEP) not only in terms of execution time and energy but also optimal architecture usage. We...
ISCA
2003
IEEE
14 years 27 days ago
2003
IEEE
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...