This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient Filter Cache as a baseline and ...
David Black-Schaffer, James D. Balfour, William J....
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...