38 search results - page 3 / 8 » Hierarchical Instruction Register Organization |
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Large register file with multiple ports, but with a minimal access time, is a critical component in a superscalar processor. Analysis of the lifetime of a logical to physical reg...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
ASAP
2000
IEEE
14 years 2 days ago
2000
IEEE
MicroSIMD architectures incorporating subword parallelism are very efficient for application-specific media processors as well as for fast multimedia information processing in gen...
IFIP
1993
Springer
13 years 11 months ago
1993
Springer
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various ...