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» Hierarchical Instruction Register Organization
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ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
14 years 1 days ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
POPL
2003
ACM
14 years 8 months ago
Bitwidth aware global register allocation
Multimedia and network processing applications make extensive use of subword data. Since registers are capable of holding a full data word, when a subword variable is assigned a r...
Sriraman Tallam, Rajiv Gupta
ICCAD
1997
IEEE
162views Hardware» more  ICCAD 1997»
13 years 12 months ago
Application-driven synthesis of core-based systems
We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraini...
Darko Kirovski, Chunho Lee, Miodrag Potkonjak, Wil...
LCTRTS
2009
Springer
14 years 2 months ago
A compiler optimization to reduce soft errors in register files
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
Jongeun Lee, Aviral Shrivastava
MICCAI
2004
Springer
14 years 8 months ago
Image Registration by Hierarchical Matching of Local Spatial Intensity Histograms
We previously presented a HAMMER image registration algorithm that demonstrated high accuracy in superposition of images from different individual brains. However, the HAMMER regis...
Dinggang Shen