Application-driven synthesis of core-based systems

We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraining most-constrained heuristic to minimize the instruction cache misses for a given application, instruction cache size and organization. Based on this performance optimization technique, we constructed a strategy to search for a minimal area processor core, and an instruction and data cache which satisfy the performance characteristics of a set of target applications. The synthesis platform integrates the existing modeling, pro ling, and simulation tools with the developed system-level synthesis tools. The e ectiveness of the approach is demonstrated on a variety of modern real-life multimedia and communication applications.

• Type: Conference
• Year: 1997
• Where: ICCAD
• Authors: Darko Kirovski, Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith
• Keywords: Hardware, ICCAD 1997, Instruction Cache, Instruction Cache Misses, Instruction Cache Size