238 search results - page 16 / 48 » Hierarchical Interconnect Circuit Models |
ISCAS
2003
IEEE
14 years 27 days ago
2003
IEEE
An efficient model-order reduction technique for general RLC networks is proposed. The method is extended from the previous projection-base moment matching method with considerin...
TVLSI
2010
13 years 2 months ago
2010
To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp ...
ICPP
2000
IEEE
14 years 23 hour ago
2000
IEEE
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are ...