238 search results - page 19 / 48 » Hierarchical Interconnect Circuit Models |
TVLSI
2002
13 years 7 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
ICCAD
2000
IEEE
14 years 1 days ago
2000
IEEE
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
VLSID
1999
IEEE
13 years 12 months ago
1999
IEEE
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...