238 search results - page 40 / 48 » Hierarchical Interconnect Circuit Models |
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional (3D) integrated circuits are proposed as one way to address this p...
TCAD
2002
13 years 7 months ago
2002
As very large scale integration (VLSI) circuit speed rapidly increases, the inductive effects of interconnect lines strongly impact the signal integrity of a circuit. Since these i...
GLVLSI
1998
IEEE
13 years 12 months ago
1998
IEEE
Important layout properties of electronic designs include interconnection length values, clock speed, area requirements, and power dissipation. A reliable estimation of those prop...
IEICET
2008
13 years 7 months ago
2008
This paper studies impact of the well edge proximity effect on digital circuit delay, based on model parameters extracted from test structures in an industrial 65nm wafer process. ...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...