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» Hierarchical Interconnect Circuit Models
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DAC
2008
ACM
13 years 9 months ago
DeMOR: decentralized model order reduction of linear networks with massive ports
Model order reduction is an efficient technique to reduce the system complexity while producing a good approximation of the input-output behavior. However, the efficiency of reduc...
Boyuan Yan, Lingfei Zhou, Sheldon X.-D. Tan, Jie C...
IADIS
2003
13 years 9 months ago
Using Opnet Modeler to Analyse Galileo Communication Networks
Galileo is a European initiative to develop and deploy an independent global satellite-based navigation system. It consists of a Medium Earth Orbit sat ellite constellation transm...
Filipa Borrego, Juan-Antonio Martinez Rosique, Man...
DAC
2005
ACM
14 years 8 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
IPPS
2009
IEEE
14 years 2 months ago
Designing multi-leader-based Allgather algorithms for multi-core clusters
The increasing demand for computational cycles is being met by the use of multi-core processors. Having large number of cores per node necessitates multi-core aware designs to ext...
Krishna Chaitanya Kandalla, Hari Subramoni, Gopala...
HPDC
2005
IEEE
14 years 1 months ago
Automatic dynamic run-time optical network reservations
Optical networking may dramatically change high performance distributed computing. One reason is that optical networks can support provisioning dynamically configurable lightpath...
John R. Lange, Ananth I. Sundararaj, Peter A. Dind...