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» Hierarchical Interconnect Circuit Models
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ICPP
1999
IEEE
13 years 12 months ago
The Index-Permutation Graph Model for Hierarchical Interconnection Networks
In this paper, we present the index-permutation (IP) graph model, and apply it to the systematic development of efficient hierarchical networks. We derive several classes of inter...
Chi-Hsiang Yeh, Behrooz Parhami
IJCAI
2007
13 years 9 months ago
Modeling When Connections Are the Problem
Most AI diagnostic reasoning approaches model components and but not their interconnections, and when they do model interconnections, they model the possibility that a connection ...
Johan de Kleer
ICCAD
2003
IEEE
141views Hardware» more  ICCAD 2003»
14 years 4 months ago
Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules
In this paper, we present a reduced order inodeling methodology, based on the utilization of optimal non-uniform grids generated by Gaussian spectral rules, for the direct passive...
Traianos Yioultsis, Anne Woo, Andreas C. Cangellar...
ICCAD
2004
IEEE
80views Hardware» more  ICCAD 2004»
14 years 4 months ago
HiSIM: hierarchical interconnect-centric circuit simulator
To ensure the power and signal integrity of modern VLSI circuits, it is crucial to analyze huge amount of nonlinear devices together with enormous interconnect and even substrate ...
Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 1 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...