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    ICCD
    1997
    IEEE
    123views Hardware» more  ICCD 1997»
    A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
    13 years 11 months ago
    A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
    Download  www.engr.uconn.edu
    Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
    John A. Chandy, Prithviraj Banerjee
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    IJON
    2007
    118views more  IJON 2007»
    Low power CMOS electronic central pattern generator design for a biomimetic underwater robot
    13 years 7 months ago
    Low power CMOS electronic central pattern generator design for a biomimetic underwater robot
    Download  www.ece.neu.edu
    — This paper, presents a feasability study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electroni...
    Young-Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin ...
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    WSC
    2007
    233views Modeling And Simulation» more  WSC 2007»
    Hierarchical planning and multi-level scheduling for simulation-based probabilistic risk assessment
    13 years 10 months ago
    Hierarchical planning and multi-level scheduling for simulation-based probabilistic risk assessment
    Download  www.informs-sim.org
    Simulation of dynamic complex systems—specifically, those comprised of large numbers of components with stochastic behaviors—for the purpose of probabilistic risk assessment f...
    Hamed Nejad, Dongfeng Zhu, Ali Mosleh
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    DAC
    1999
    ACM
    147views Computer Architecture» more  DAC 1999»
    Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching
    14 years 8 months ago
    Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching
    Download  vlsi.ece.wisc.edu
    Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
    Chung-Ping Chen, Noel Menezes
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    DAC
    2004
    ACM
    129views Computer Architecture» more  DAC 2004»
    A SAT-based algorithm for reparameterization in symbolic simulation
    14 years 8 months ago
    A SAT-based algorithm for reparameterization in symbolic simulation
    Download  www.kroening.com
    Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
    Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening
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