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» Hierarchical Simulation of a Multiprocessor Architecture
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DAC
2010
ACM
13 years 7 months ago
A correlation-based design space exploration methodology for multi-processor systems-on-chip
Given the increasing complexity of multi-processor systems-onchip, a wide range of parameters must be tuned to find the best trade-offs in terms of the selected system figures of ...
Giovanni Mariani, Aleksandar Brankovic, Gianluca P...
ISCA
2005
IEEE
147views Hardware» more  ISCA 2005»
14 years 1 months ago
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
DAC
2006
ACM
13 years 9 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
IFIP
1999
Springer
13 years 11 months ago
Experimental comparison of control architectures
Most control systems of flexible production cells have a hierarchical structure. They become very complicated and difficult to maintain and modify when the underlying production c...
J. M. van de Mortel-Fronczak, J. P. M. Schmitz, J....
CODES
2009
IEEE
14 years 2 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...