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» Hierarchical Simulation of a Multiprocessor Architecture
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WSC
2008
13 years 10 months ago
PLCStudio: Simulation based PLC code verification
Proposed in this paper is the architecture of a PLC programming environment that enables a visual verification of PLC programs. The proposed architecture integrates a PLC program ...
Sang C. Park, Chang Mok Park, Gi-Nam Wang, Jonggeu...
FPL
2005
Springer
136views Hardware» more  FPL 2005»
14 years 1 months ago
Architecture-Adaptive Routability-Driven Placement for FPGAs
Current FPGA placement algorithms estimate the routability of a placement using architecture-specific metrics. The shortcoming of using architecture-specific routability estimates ...
Akshay Sharma, Carl Ebeling, Scott Hauck
IPPS
2009
IEEE
14 years 2 months ago
A metascalable computing framework for large spatiotemporal-scale atomistic simulations
A metascalable (or “design once, scale on new architectures”) parallel computing framework has been developed for large spatiotemporal-scale atomistic simulations of materials...
Ken-ichi Nomura, Richard Seymour, Weiqiang Wang, H...
DAC
2004
ACM
14 years 8 months ago
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics
Capacitance extraction is an important problem that has been extensively studied. This paper presents a significant improvement for the fast multipole accelerated boundary element...
Shu Yan, Vivek Sarin, Weiping Shi
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
14 years 2 months ago
On-chip communication architecture exploration for processor-pool-based MPSoC
— MPSoC is evolving towards processor-pool (PP)-based architectures, which employ hierarchical on-chip network for inter- and intra-PP communication. Since the design space of PP...
Young-Pyo Joo, Sungchan Kim, Soonhoi Ha