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» Hierarchical Simulation of a Multiprocessor Architecture
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PPL
2008
185views more  PPL 2008»
13 years 7 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
ICPP
2009
IEEE
14 years 2 months ago
Bank-aware Dynamic Cache Partitioning for Multicore Architectures
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
14 years 13 hour ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
GLOBECOM
2009
IEEE
14 years 2 months ago
Hierarchical Network Formation Games in the Uplink of Multi-Hop Wireless Networks
— In this paper, we propose a game theoretic approach to tackle the problem of the distributed formation of the hierarchical network architecture that connects the nodes in the u...
Walid Saad, Quanyan Zhu, Tamer Basar, Zhu Han, Are...
WSNA
2003
ACM
14 years 26 days ago
Role-based hierarchical self organization for wireless ad hoc sensor networks
Efficiently self organizing a network hierarchy with specific assignment of roles (or tasks) to sensors based on their physical wireless connectivity and sensing characteristics ...
Manish Kochhal, Loren Schwiebert, Sandeep K. S. Gu...