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DATE
2004
IEEE
129views Hardware» more  DATE 2004»
14 years 2 months ago
On the Design and Verification Methodology of the Look-Aside Interface
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
Ali Habibi, Asif Iqbal Ahmed, Otmane Aït Moha...
DCOSS
2006
Springer
14 years 2 months ago
When Birds Die: Making Population Protocols Fault-Tolerant
In the population protocol model introduced by Angluin et al. [2], a collection of agents, which are modelled by finite state machines, move around unpredictably and have pairwise ...
Carole Delporte-Gallet, Hugues Fauconnier, Rachid ...
ASPDAC
1995
ACM
130views Hardware» more  ASPDAC 1995»
14 years 2 months ago
Design for testability using register-transfer level partial scan selection
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa...
WSC
2008
14 years 22 days ago
A new method for bottleneck detection
This paper presents a new method to identify and rank the bottlenecks in a manufacturing system. The proposed method is based on performance related data that are easy to capture,...
Sankar Sengupta, Kanchan Das, Robert P. VanTil
CONCUR
2008
Springer
14 years 6 days ago
R-Automata
R-automata are finite state machines extended with counters which can be incremented or reset to zero along the transitions. The universality question asks whether there is a cons...
Parosh Aziz Abdulla, Pavel Krcál, Wang Yi