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» Hierarchical Test Generation with Built-In Fault Diagnosis
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ITC
2003
IEEE
149views Hardware» more  ITC 2003»
14 years 25 days ago
On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures
Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Regist...
Ramesh C. Tekumalla
ICCD
2005
IEEE
124views Hardware» more  ICCD 2005»
14 years 4 months ago
Accurate Diagnosis of Multiple Faults
In this paper, we propose a diagnostic test generation method in conjunction with an efficient sequential SAT-based diagnosis procedure to precisely identify multiple defective si...
Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
13 years 11 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
ECAI
2008
Springer
13 years 9 months ago
Test Generation for Model-Based Diagnosis
This article formalises the dual problem to model-based diagnosis (MBD), i.e., generating tests to isolate multiple simultaneous faults. Using a standard propositional MBD framewo...
Gregory M. Provan
TCAD
2002
134views more  TCAD 2002»
13 years 7 months ago
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures
As IC densities are increasing, cluster-based FPGA architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-based architecture is one in which...
Ian G. Harris, Russell Tessier